a. Field of the Invention
The present invention is in the field of integrated circuits, and in particular involves field effect transistors.
b. Description of the Related Art
A type of semiconductor transistor known as a field effect transistor, or FET, includes three terminals: (1) a source; (2) a drain; and (3) a gate. When a threshold voltage is applied to the gate, a “field effect” takes place in a region of semiconductor material under the gate, called the “gate region.” The effect is either a build up of charge or a depletion of charge in the gate region. Which event occurs depends on the doping conductivity type of the gate region and the polarity of the gate voltage. The build up or depletion of charges creates a channel under the gate that electrically connects the source and the drain. If a channel is present while the drain region is biased with a voltage, and the source region is grounded relative to the drain region, then a current will flow through the channel between the drain and source regions.
Among the various types of FETs are enhancement mode (E-mode) and depletion mode (D-mode) transistors. An E-mode transistor is non-conductive when the gate voltage is zero or negative. For this reason, an E-mode transistor is classified as a “normally off” transistor. An E-mode transistor is driven into conduction by bringing the gate voltage positive with respect to the source voltage. In a D-mode transistor, by contrast, there is conduction even with zero gate voltage, provided that the drain region is biased with a voltage, and the source region is grounded relative to the drain region. For this reason, D-mode transistors are classified as “normally-on” transistors. A D-mode transistor is made non-conductive by bringing the gate voltage negative with respect to the source voltage.
One type of FET that is useful for high frequency applications is high electron mobility transistor (HEMT). HEMT devices may be formed as either enhancement mode or depletion mode devices, and often are formed from Group III-V materials, such as gallium arsenide (GaAs) and indium phosphide (InP).
Generally, a HEMT includes a channel layer that is overlaid by a spacer layer that is overlaid by a barrier layer. The spacer and barrier layers are formed of a wide band gap semiconductor material. The channel layer is formed of a narrow band gap semiconductor material. Due to the conduction band discontinuity at the junction between these dissimilar semiconductor materials, which is called a “heterojunction,” electrons are injected from the barrier layer into the channel layer during operation of the transistor. The electrons are confined to move in a plane parallel to the heterojunction due to the relatively wider bandgap of the barrier layer. The electrons move more easily through the channel layer of a HEMT device than through the channel of an ordinary FET. As a result, HEMT devices can operate at high speed and low noise levels.
In certain applications, it is desirable to form semiconductor devices, such as direct-coupled FET logic devices, that monolithically integrate a D-mode transistor with an E-mode transistor in a single integrated circuit. FIG. 1 discloses a conventional monolithically integrated D-mode/E-mode transistor device 1 that includes a D-mode transistor 2 that is monolithically integrated with an E-mode transistor 3 in a multi-layer structure 5. In this particular example, each of the D-mode and E-mode transistors 2, 3 are a type of HEMT known as a pseudo-morphic high-electron mobility transistor, or pHEMT. While the D-mode transistor 2 and the E-mode transistor 3 are shown as being laterally adjacent to each other for ease of view, the D-mode and E-mode transistors 2, 3 may be disposed away from each other in different regions of the integrated circuit.
Multi-layer structure 5 includes a semiconductor substrate 12 that is formed of undoped GaAs. Disposed in successive layers over semiconductor substrate 12 are various epitaxial semiconductor layers, including: a buffer layer 14; channel and spacer layers 16; an E-mode barrier layer 18; an E-mode etch stop layer 20; a D-mode barrier layer 22; a D-mode etch stop 24; a wide recess transition layer 26; and an ohmic contact layer 28. Note that there are two barrier layers and two etch stop layers.
The D-mode transistor 2 and the E-mode transistor 3 each include a metal source contact 38 and a metal drain contact 40 on an upper surface of the ohmic contact layer 28. Each transistor 2, 3 is electrically isolated within a respective hollow column of implanted ions, depicted as isolation region 6, that surrounds the respective transistor 2, 3. The sidewall of the respective isolation region 6 around each transistor 2, 3 extends downward from the upper surface of ohmic contact layer 28 through the buffer layer 14.
Laterally between the source and drain terminals 38, 40 of both of the D-mode and E-mode transistors 2, 3 is a metal gate contact of the respective transistor 2, 3. The D-mode and E-mode gate contacts 30, 34 are disposed in respective D-mode and E-mode gate recesses 32, 36 that extend into multi-layer substrate 5 from the upper surface of ohmic contact layer 28. The D-mode and E-mode gate contacts 30, 34 are coupled to different ones of the interior semiconductor layers of multi-layer structure 5 at points vertically below the ohmic contact layer 28.
In particular, the D-mode gate contact 30 of D-mode transistor 2 is coupled to an upper surface of D-mode barrier layer 22 within the D-mode gate recess 32. The semiconductor sidewall 33 of the D-mode gate recess 32 tapers inwardly going from the upper surface of ohmic contact layer 28 downward toward D-mode barrier layer 22. In addition, the sidewall 33 is stepped, so as to form a wide recess ledge 46 at the upper surface of wide recess transition layer 26. The presence of the wide recess ledge 46 is included to enhance the breakdown voltage of the D-mode transistor 2.
Similarly, the metal gate contact 34 of E-mode transistor 3 is coupled to an upper surface of E-mode barrier layer 18 within the E-mode gate recess 36. The semiconductor sidewall 37 of the E-mode gate recess 36 also tapers inwardly going from the upper surface of ohmic contact layer 28 downward toward the D-mode barrier layer 22. In addition, the sidewall 37 is stepped, so as to form a wide recess ledge 46 at the upper surface of wide recess transition layer 26. The presence of the wide recess ledge 46 is included to enhance the breakdown voltage of the E-mode transistor 3.
As shown in FIG. 1, the E-mode gate recess 36 and the E-mode gate contact 34 extend vertically deeper into multi-layer structure 5 than the D-mode gate recess 32 and D-mode gate contact 30, because the E-mode barrier layer 18 to which the E-mode gate contact 34 is coupled vertically below the D-mode barrier layer 22 and the E-mode etch stop layer 20.
To form the stepped D-mode gate recess 32, a plurality of photolithography and etch steps are required, including: (1) a first selective etch step that etches the ohmic contact layer 28 through a first photoresist mask and stops on wide recess transition layer 26; (2) a second selective etch step that etches the wide recess transition layer 26 through a second photoresist mask and stops on D-mode etch stop layer 24; and (3) a third selective etch step that etches the D-mode etch stop layer 24 through the second photoresist mask and stops on D-mode barrier layer 22.
Likewise, a plurality of photolithography and etch steps are required to form the E-mode gate recess 36, including: (1) a first selective etch step that etches the ohmic contact layer 28 through a first photoresist mask and stops on wide recess transition layer 26; (2) a second selective etch step that etches wide recess transition layer 26 through a second photoresist mask and stops on D-mode etch stop layer 24; (3) a third selective etch step that etches D-mode etch stop layer 24 through the second photoresist mask and stops on D-mode barrier layer 22; (4) a fourth selective etch step that etches the D-mode barrier layer 22 through the second photoresist mask and stops on E-mode etch stop layer 20; and (5) a fifth selective etch step that etches the E-mode etch stop layer 20 through the second photoresist mask and stops on E-mode barrier layer 18.
The gate contacts 30, 34 of the D-mode and E-mode transistors 2, 3, respectively, have the same structure, and consist of several successive metal layers, including: (1) a thin first layer of titanium (Ti) in contact with the surface of barrier layers 22, 18, respectively; (2) a thin second layer of platinum (Pt) on the Ti layer; and (3) a relatively-thick layer of gold (Au) on the Pt layer. The source and drain contacts 38, 40 also are formed of several successive metal layers, including: (1) a first layer of Au in contact with the upper surface of ohmic contact layer 28; (2) a second layer of nickel (Ni) on the Au layer; (3) a third layer of germanium (Ge) on the Ni layer; and (4) a fourth layer of Au on the Ge layer.
The D-mode and E-mode gate recesses 32, 36 are typically filled with a dielectric material around the metal gate contacts 30, 34. The dielectric material may be silicon dioxide or silicon nitride. Metal interconnects are coupled to the top surface of the gate contacts 30, 34, the source contacts 38, and the drain contacts 40 to complete the D-mode and E-mode transistors 2, 3.
The conventional monolithic integrated E-mode/D-mode transistor device 1 of FIG. 1 has several problematic aspects. First, the multi-layer structure 5 includes a multiplicity of semiconductor layers, including two etch stop layers 20, 24 and two barrier layers 18, 22. The greater the number of layers, the greater the cost and complexity of the multi-layer structure 5. This leads to additional cost and complexity in the transistor fabrication process. For instance, the process for forming the E-mode gate recess 36 of FIG. 1 involves at least five selective etch steps.
In addition, the E-mode etch stop layer 20, which is necessary to the making of E-mode transistor 3, is beneath the D-mode gate contact 30 and barrier layer 22 of the D-mode transistor 2. Because manufacturing tolerances related to the thickness of the various epitaxial layers of the multi-layer structure 5 are up to 5% for a given epitaxial vendor and epitaxial growth machine, the structure of the multi-layer structure 5 beneath D-mode transistor 2 is variable. Unfortunately, such variations in the placement of E-mode etch stop layer 20 will lead to variability in the performance of the D-mode transistor 2 from wafer to wafer. In addition, the presence of the E-mode etch stop layer 24 beneath the D-mode gate contact 30 can also lead to other undesirable conditions, such as interfacial defects, interface roughness, non-uniformity, conduction and valence band offsets, and different material resistivities. These conditions also will degrade the performance of the D-mode transistor 2.
The performance of the E-mode transistor 3 also is compromised in the conventional design. For instance, a certain degree of overetch is required to ensure that the E-mode etch stop layer 20 is reached during the step of etching through D-mode barrier layer 22. During the overetching step, etching in the vertical direction proceeds slowly because of the selectivity of the etchant to E-mode etch stop layer 20. On the other hand, etching in the lateral direction through the D-mode barrier layer 22 proceeds unabated. As a result, the perimeter of the partially-completed E-mode gate recess 36 at the exposed surface of the E-mode etch stop layer 20 is greater than desired. The subsequent etch step that etches through E-mode etch stop layer 20 therefore exposes a larger-than-desired area of the upper surface of E-mode barrier layer 18. Since the E-mode gate contact 34 only partially covers the exposed upper surface of the E-mode barrier layer 18 within E-mode gate recess 36, an ungated region 44 on the surface of E-mode barrier layer 18 is formed. Control of the extent of the ungated region 44 is difficult due to variations in the epitaxial layer thicknesses and etch dependencies on the feature size.
The relatively-large surface area of the semiconductor sidewall 37 and ungated region 44 of the E-mode gate recess 36 is problematic. These surfaces, which are covered by a native oxide due to exposure to the air, possess interface traps and defects due to the abrupt termination of the regular crystal lattice, which in turn causes dangling bonds, defects, and surface states to form. The surface states will deplete the underlying semiconductor material of charge carriers, and can effectively cause the E-mode transistor 3 to be permanently off irrespective of the gate voltage applied to the E-mode gate contact 34.
Accordingly, a new approach to achieving a monolithically integrated D-mode/E-mode FET device is desirable.